Nonvolatile memory cells that are electrically programmable and erasable can be realized as charge-trapping memory cells, which comprise a memory layer sequence of dielectric materials with a memory layer between confinement layers of dielectric material having a larger energy band gap than the memory layer. The memory layer sequence is arranged between a channel region within a semiconductor body and a gate electrode provided to control the channel by means of an applied electric voltage. Examples of charge-trapping memory cells are the SONOS memory cells, in which each confinement layer is an oxide and the memory layer is a nitride of the semiconductor material, usually silicon (see U.S. Pat. No. 5,768,192 and U.S. Pat. No. 6,011,725, which are incorporated herein by reference).
Charge carriers moving from source to a drain through the channel region are accelerated and gain enough energy to be able to penetrate the lower confinement layer and to be trapped within the memory layer. The trapped charge carriers change the threshold voltage of the cell transistor structure. Different programming states can be read by applying the appropriate reading voltages.
Charge-trapping memory devices can be provided with buried bitlines, which electrically connect the source/drain regions of the memory cells. A memory layer sequence, typically an oxide-nitride-oxide layer sequence, is located above the channel regions between corresponding source/drain regions. Above the buried bitlines, a thick oxide is formed as an electrically insulating region, especially to separate the gate electrode sufficiently from the buried bitlines. The memory layer sequence is confined to the channel region and overlaps the source/drain regions only slightly.
In the course of the production of the insulating oxide, a bird's beak shape is produced at the lateral edges of the memory layer sequence. Here, the problem arises that the memory layer, typically the silicon nitride layer, is not sufficiently surrounded by the confinement layers in order to provide a reliable charge-trapping. Especially the application of higher temperatures and gate stress can lead to a charge loss in this region. This may lead to a drift of the read current of the memory cell. If electrons are used as charge carriers to be trapped in the memory layer, an injection of holes originating from the gate electrode into the nitride of the memory layer may occur, and the holes may diffuse towards the trapped electrons and thus effect a charge compensation canceling the programmed state.
This problem may be obviated by a deposition of an additional oxide layer to increase the thickness of the confinement layer at the edges of the memory layer sequence. As this oxide layer has to be deposited before the formation of the gate electrode stack, the production process grows considerably more complex, and the final thickness variations of the memory layer sequence are also increased by this method.